219 / 2017-11-21 15:13:12
A 1MHz Gate Driver for Parallel Connected SiC MOSFETs with Protection Circuit
Final Paper
Xuchao Jiang / Xidian University
Yimeng Zhang / Xidian University
Design of a 1MHz SiC MOSFET gate driver circuit have been implemented in this paper, which enhances the reliability of parallel-connected
SiC MOSFETs in high frequency applications. Improvements have been made for high-speed overcurrent protection circuit. The fault status can be latched and counted for both overcurrent protection and over-voltage and under-voltage protection of MOSFET gate. In addition, dynamic balancing current sharing structure is proposed for high-speed SiC MOSFET in parallel application. Balanced current sharing can be achieved by means of current feedback and switching delay time compensation. The proposed schemes are verified through experimental results.
Important Date
  • Conference Date

    May 17

    2018

    to

    May 19

    2018

  • Dec 08 2017

    Abstract Submission Deadline

  • Jan 30 2018

    Abstract Notification of Acceptance

  • Feb 10 2018

    Draft paper submission deadline

  • Feb 10 2018

    Final Paper Deadline

  • May 19 2018

    Registration deadline

Sponsored By
IEEE
Organized By
Xi'an Jiaotong University
Xidian University
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