IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia 2018)

274 / 2017-12-05 16:08:21

A Study of the Performances Degradation for 4H-SiC Traps-stressed UMOSFET using Experimental and Simulation Methods

UMOSFET,trap,mobility,leakage current

Plenary track > Device characterization and modeling

In this work, we analyze the electrical characteristics of 4H-SiC traps-stressed UMOSFET. A reasonable fit to the experimental data is obtained by a 2-D numerical simulator. The calculation results show that the traps-assisted acoustic-phonon scattering would cause the mobility degradation at high gate voltage. Based on the simulation model, the non local tunneling barrier can be further reduced at the hetero interface of trench bottom due to the electron trapping mainly resulting from the source terminal. Thus, the gate leakage current increases under high gate-bias stress, which is consistent with the experimental results. In addition, the energetic hot carriers may be accelerated and enter the thinner oxide region at high drain voltage, which gives rise to premature breakdown in 4H-SiC UMOSFETs.