IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia 2018)

275 / 2017-12-05 16:24:49

Simulation of a Short-Channel 4H-SiC UMOSFET with Buried p Epilayer for Low Oxide Electric Field and Switching Loss

Silicon Carbide,trench MOSFET,electric field,switching loss

Plenary track > Device characterization and modeling

In this study, a 4H-SiC UMOSFET structure, which can significantly reduce both the electric field in the gate dielectric and the total switching loss, is characterized and analyzed by simulation. The presented structure features a buried p layer (BPL) inside the drift region and an n implanted region (Nimplant) under the trench bottom. Meanwhile, a channel length of less than 0.5 μm can be obtained with the shielding of the BPL and the Nimplant region. The peak electric field of 1.03 MV/cm at the gate trench is reduced by 78.1% and 55.6% in comparison to the peak electric fields in the conventional UMOSFETs without and with bottom p well (BPW), respectively. In comparison to the conventional UMOSFETs with and without BPW, the total switching loss of 18.84 mJ/cm2 is decreased by 28% and 74%, respectively. Baliga’s figure of merit is BFOM = 1100 MW/cm2, which shows the very high potential of the proposed UMOSFET structure for medium voltage power-electronic applications.