287 / 2017-12-07 15:08:22
An Integrated Gate Driver with Active Delay Control Method for Series Connected SiC MOSFETs
SiC MOSFET,series connected,voltage balance,delay line,auxiliary driver
Final Paper
Panrui Wang / Shandong University
Feng Gao / Shandong University
An integrated gate driver with active delay control method for series connected SiC MOSFETs is presented in this paper to achieve voltage balance. A RC voltage divider is applied to detect the voltage between drain and source terminals, and the voltage signal is fed into a high speed AD converter through a voltage follower. With the isolation of optocoupler, the voltage data is transferred to the main controller. The controller generates PWM pulses and computes the delay time that should be applied for each SiC MOSFET drive signal with the voltage data to maintain the voltage balance. The delay action is implemented by a delay line IC. The proposed gate driver provides a closed loop control for series connected SiC MOSFETs. It can effectively balance the voltage without slowing down the switching speed or inducing extra losses, and the effectiveness of the proposed gate driver has been verified by experimental results.
Important Date
  • Conference Date

    May 17

    2018

    to

    May 19

    2018

  • Dec 08 2017

    Abstract Submission Deadline

  • Jan 30 2018

    Abstract Notification of Acceptance

  • Feb 10 2018

    Draft paper submission deadline

  • Feb 10 2018

    Final Paper Deadline

  • May 19 2018

    Registration deadline

Sponsored By
IEEE
Organized By
Xi'an Jiaotong University
Xidian University
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