298 / 2017-12-07 23:43:40
Extra Device Capacitance in Three-level Converters and Loss Re-evaluation via Conventional DPT Data
Final Paper
Bo Liu / University of Tennessee, Knoxville
Edward Jones / University of Tennessee, Knoxville
Ren Ren / University of Tennessee, Knoxville
Zheyu Zhang / University of Tennessee, Knoxville
Fred Wang / University of Tennessee, Knoxville
Daniel Costinett / University of Tennessee, Knoxville
In this paper, an extra junction capacitance and its associated switching commutation path are found in three-level ac/dc converters, which were overlooked due to the off-state of the related device within half line cycle. The impact of this effect on power loss is analyzed, showing an underestimated switching loss in the traditional loss calculation of three-level converters. Through a proposed loss re-evaluation approach based on energy data of conventional double pulse tester (DPT), the corrected switching loss matches experimental results obtained from a 650 V enhancement-mode Gallium Nitride (GaN) based Vienna-type rectifier. And the dominant extra switching loss is found to be Coss loss instead of overlap loss in WBG converters. Thus, the effect is severe in high-speed WBG three-level converters.
Important Date
  • Conference Date

    May 17

    2018

    to

    May 19

    2018

  • Dec 08 2017

    Abstract Submission Deadline

  • Jan 30 2018

    Abstract Notification of Acceptance

  • Feb 10 2018

    Draft paper submission deadline

  • Feb 10 2018

    Final Paper Deadline

  • May 19 2018

    Registration deadline

Sponsored By
IEEE
Organized By
Xi'an Jiaotong University
Xidian University
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