3 / 2018-06-12 17:14:01
New QCA T flip flop and 4-bit counter structures
TFlip-Flop designing,-QCA-,optimized counter,nanotechnology
Draft Pending
Mostafa sadeghi / Young Researchers and Elite Club, Zavareh Branch Islamic Azad University, Zavareh, IRAN Mostafa13h@g
Problems of shrinking CMOS transistors’ sizes in order to miniaturize the circuit & decrease the power consumption of integrated circuits specially in digital integrated circuit (VLSI) persuaded the researchers to use the newer & better ways for building the logic gates. One of the proposed methods is use of quantum cellular automata which is presented to design the logic circuits and in recent years, has paid attention to it. In this paper, we could design the optimized T Flip-Flop model from the used cell numbers point of view by QCA technology so that we achieve an optimized 4 bit counter, thereby the occupied space would be shrunk.
Important Date
  • Conference Date

    Aug 13

    2018

    to

    Aug 14

    2018

  • Jan 31 2018

    Draft paper submission deadline

  • Apr 01 2018

    Draft Paper Acceptance Notification

  • Jun 30 2018

    Final Paper Deadline

  • Aug 14 2018

    Registration deadline

Sponsored By
IEEE
Organized By
Universiti Teknologi Petronas
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