The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

391 / 2019-02-14 20:04:33

Mix-signal Common Mode Charge Error Calibration Circuit for 14-bit 210MSPS Charge-Domain ADC

Pipelined analog-to-digital converter; Charge- domain; For-ground calibration; Low power；Common-mode charge

Plenary track > Analog Circuits

A mix-signal high precision common mode charge error calibration circuit is proposed. Common mode charge errors caused by the deviation of the charge transfer cutoff voltage of boosted charge transfer introduced by PVT variation, the variation of input common mode charge and the capacitor mismatch the variation of reference voltage in pipelined sub-stage circuit, can be compensated precisely by the proposed calibration circuit for charge domain pipelined ADCs. Based on the proposed calibration circuit, a 14-bit 210MS/s charge domain pipelined ADC is designed and realized in a 1P6M 0.18μm CMOS process. Test results show the ADC achieves the SNR of 71.5dBFS and the SFDR of 85.4dB, with 30.1MHz input at 210MS/s, while the ADC core consumes the power consumption of 205mW.