The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

394 / 2019-01-28 10:41:53

A Novel Hardware/software Co-design for An Efficient RSA System

Hardware/software co-design,RSA,SOS

Plenary track > Digital Circuits

RSA is a secure, high quality, asymmetric key algorithm which is widely used today. To realize high performance and high flexibility at the same time, measures of hardware/software co-design are taken. Four schemes of RSA algorithm based on different partition of software and hardware are implemented : flexibility-orientated, performance-orientated ,balanced one and pure hardware implementation. Some optimization attempts are taken. The bottleneck of SOS algorithm is analyzed and accelerated by ASM language to reach 75.9% running time reduction. The performance-orientated scheme put computation-intensive parts into hardware and communication part into software to take the advantage of each one. It is even faster than pure hardware scheme in decryption. The cycle of the this scheme is less than 2% of the pure software scheme.