The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

461 / 2019-03-14 08:44:19

12.5GHz clock generator for 4x100Gbps high speed serial interface

Two-stage phase-locked loop,sample-locked loop,multi-channel high-speed serial interface

Plenary track > Analog Circuits

In order to alleviate the problem of excessive noise and excessive power consumption introduced by long-distance transmission of high-frequency clock signals in multi-channel SerDes, this paper designs a two-stage phase-locked loop for multi-channel. The first stage uses a charge pump phase-locked loop structure, and the second stage uses a sample-locked loop structure. The clock generator circuit has an overall power consumption of 100 mW, the phase-controlled oscillator circuit has a phase noise of -79 dBc/Hz at 1 MHz, and the clock signal jitter generated by the phase-locked loop circuit is 2.7 ps overall.