The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

465 / 2019-02-27 21:02:18

Comparator Delay Optimization for Hysteretic-based Controlled High Frequency Buck Converters in Mobile Applications

buck converter, high frequency, hysteretic control

Plenary track > Analog Circuits

A hysteretic based DC-DC buck converters with comparator optimization is presented in this paper. To decrease the size of passive component and fast the response speed, higher operating frequency is adapted, which demands the comparator smaller transmission delay. The comparator is designed by adding an offset to reduce the delay when its differential inputs are small. By using 180nm BCD process, the buck converter with optimized comparator is simulated. The simulations show that the buck convertor could work with 50MHz with a high output current 1.5A and have fast response when the load changes.