The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

494 / 2019-03-13 15:11:13

A 5/10 Gb/s Dual-Mode NRZ/PAM4 CDR in 65-nm CMOS

NRZ; PAM4; CDR; digital loop filter; adaptive threshold voltage; clock jitter

Plenary track > Wireless Communication

A dual-mode clock and data recovery (CDR) circuit based on phase interpolator (PI) in 65nm CMOS is presented. CDR can recover clock from quadrature phase shift keying (QPSK) modulated signal in non-to-zero (NRZ) mode, and 16 quadrature amplitude modulation (QAM) signal in 4 pulse amplitude modulation (PAM4) mode. An adaptive threshold voltage loop for PAM4 signal is proposed. Simulation results show that CDR can track maximum ±1000ppm frequency offset between transmitter and receiver in two modes, and the jitter of the locked clock is 45.2ps in NRZ mode and 47.8ps in PAM4 mode, respectively.