The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

527 / 2019-03-08 15:55:23

A 56-Gb/s PAM4 Continuous-Time Linear Equalizer in 40-nm CMOS Technology

CTLE,capacitive degeneration,inductive peaking,inverter-based TIA,56-Gb/s PAM4 signal

Plenary track > Wireless Communication

This design presents a 56-Gb/s PAM4 CTLE in 40-nm CMOS. By adopting capacitive degeneration, inductive peaking and inverter-based TIA, the CTLE achieves a maximum peaking frequency at 24 GHz, DC-gain at − 0.3 dB and 8-dB gain boosting at high frequency from a 1-V voltage supply, which can recover the eye diagram of the 56-Gb/s PAM4 signal form distortion due to the 13-dB channel loss at high frequency.