The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

547 / 2019-03-14 17:18:15

An Efficient Methodology of Building Power System on Chip

power SoC, voltage domain, PSO, voltage drop

Plenary track > Power Electronics

The regulator number and location are critical issues in the design of power system on chip. In order to achieve optimized number and location of the regulators, an efficient methodology of building power system on chip is proposed. All loads are firstly divided into their own voltage domain, where only one regulator supplies power. The voltage domain is built and continues developing, till the sum of the load current exceeds the maximum output current of regulator. The optimized location of regulator is calculated by the particle swarm optimization (PSO). The time and memory required are reduced. The proposed algorithm has been realized by MATLAB. The results were verified by IBM power grid analysis benchmarks. Compared with the IBM benchmarks’ own power distribution, voltage drop is decreased by the proposed algorithm.