The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

560 / 2019-03-14 21:51:24

A High Speed Extension Field Multiplier forPairing Acceleration

pairing computation,residue number system,hardware implmentation

Plenary track > Digital Circuits

In this paper, we present a high performance extension field multiplier for pairing acceleration on reconfigurable device. It is shown that combining Residue Number System (RNS), which is designed for concurrent architecture and modern FPGA programmable logic array. The parallelism of RNS can be fully exploited. The proof of concept is implemented on a Xilinx Ultrascale+ FPGA, which takes 352 DSPs and accomplish a $\mathbb{F}_{p^6}$ multiplication in 44 cycles at a 500MHz clock frequency.