The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

635 / 2019-03-20 11:12:40

A Platform with JTAG Debugging of SoC Based on System Level Verification

SoC, verification, GUI, JTAG

Plenary track > Digital Circuits

This paper presents an integrated platform with a GUI (Graphic User Interface) which realizing the JTAG (Joint Test Action Group) debugging for the internal of SoC (System on Chip) and used IP. This Platform has been successfully applied to different structures of chips with good portability, flexibility, and usability. The method used in the construction of platform brings benefits for the verification process.