The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

665 / 2019-04-09 21:48:13

An Improved Color Attenuation Priori Dehazing Algorithm and Its Hardware Implementation

Image dehazing, color attenuation priori, hardware architecture, FPGA

Plenary track > Algorithm

An improved color attenuation priori dehazing algorithm is proposed in this paper. The performance of the improved algorithm is tested with MATALAB program. The hardware architecture for the improved algorithm is designed, the RTL codes of the architecture are programed, simulated, and synthesized to Altera’s FPGA. Experiment results show that the improved algorithm is efficient for image dehazing and the hardware architecture designed in this paper is correct.