The 15th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

667 / 2019-04-09 21:57:56

Hardware Implementation of Census Stereo Matching Algorithm

Census stereo matching, adaptive transform window, hardware architecture, FPGA

Plenary track > Algorithm

A census stereo matching algorithm with adaptive transform window is presented in this paper, the hardware architecture of the algorithm is designed, the RTL codes of the architecture are simulated and synthesized to Altera’s FPGA, the system is tested on FPGA development board. The experimental results show that for image pairs with a resolution of 640×480, the final processing speed of the algorithm on the FPGA can reach 32fps, which can meet the general real-time requirements.