2021 9th International Symposium on Next Generation Electronics (ISNE2021)

102 / 2020-08-04 16:52:50

A 1ps Resolution Two-Step Time-to-digital Converter Using Parallel Digital-to-time Converters

TDC, DTC, Two-step structure, High resolution

Integrated Circuits and Systems > Analog and Mixed-Signal Circuits and Systems

A two-step time-to-digital converter (TDC) based on digital-to-time converter (DTC) is proposed in this paper. Two-step structure reduces by half the number of the flip-flops and the delay cells, thus largely lowering the power consumption and the chip area. This architecture adopts DTC instead of normal delay cell, which allows for the fine tuning of the DTC's delay time by the delay control words(DCW). By setting the neighboring DTC's delay time it can keep the TDC's resolution constant and reach 1ps. This 4-bit TDC architecture has been designed and simulated in 130nm CMOS process. The power consumption is about 0.7mW; the resolution is 1ps and the core area is about 0.017mm2.