2021 9th International Symposium on Next Generation Electronics (ISNE2021)

80 / 2020-04-12 09:54:13

A 12-bit 100-Msps DAC with 75.3 dB SFDR Using Randomized Biasing Current Source Selection for Real-time FOG Systems

DAC,current sense,mismatch,random number generation,return to zero

Renewable and Sustainable Energy Device and Materials > Transparent and Flexible Optoelectronics

In this investigation, a randomized current source selection approach to reduce the current mismatch for
a 12-bit current steering DAC (digital to analog converter) particularly designed for
the applications in FOG (fiber optic gyroscope) systems is demonstrated with TSMC 40 nm CMOS technology. The
proposed randomized selection and mismatch reduction approach takes advantage of a near wide-bandwidth
white noise generator to generate an unpredictable seed for digital PRNG (pseudo-random number generator)
such that the correlation of the selected current sources between adjacent conversions is drastically
reduced. Not only is the mismatch of current sources reduced, the dynamic performance, namely SFDR
(spur-free dynamic range), is improved. Besides, RTZ (return to zero) is carried out by individual
single logic gates to reduce the delay as well as the chip area. Based on post-layout simulations,
the conversion rate is over 100 Mbps, 32.81 mW at 0.9 V supply voltage. INL and DNL are 1.940 and 0.080,
respectively. Most important of all, SFDR is found to be 76.80 dBc at fin=10MHz, which is
1/10 of the system clock rate, to attain over 11 bits of ENOB (effective number of bits).