1752 / 2020-10-15 20:24:11
Selective Harmonic Elimination Control for Cascaded Digital Power Amplifier
selective harmonic elimination, interior point method, dead-time effect elimination
Draft Accepted
Junyao Tu / Huazhong University of Science and Technology
Hengyang Liu / Huazhong University of Science and Technology
Wubin Kong / Huazhong University of Science and Technology;State Key Laboratory of Advanced Electromagnetic Engineering and Technology
In this paper, the selective harmonic elimination (SHE) strategy for cascaded digital power amplifier is derived and proposed. To solve the problem of slow iteration speed or even non-convergence of the traditional iterative method when the number of levels or the number of harmonic elimination equations is large, a new solution method based on "interior point method” is introduced. In practical application the dead-time cannot be avoided, so the impact of dead-time on selective harmonic elimination strategy is also analyzed. Based on the relationship between output voltage and current during dead-time, the control method of “flexible insertion of dead-time on line” is proposed, which can significantly weaken the dead-time effect on selective harmonic elimination strategy in practice.
Important Date
  • Conference Date

    Nov 02

    2020

    to

    Nov 04

    2020

  • Oct 27 2020

    Draft paper submission deadline

  • Nov 03 2020

    Contribution Submission Deadline

  • Nov 04 2020

    Registration deadline

  • Nov 17 2020

    Final Paper Deadline

Sponsored By
IEEE IAS Student Chapter of Huazhong University of Science and Technology (HUST)
Organized By
Huazhong University of Science and Technology
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