A Novel Low Parasitic Inductance SiC Power Module Based on Symmetrical Planar Packaging Structure and Integrating the Laminated Busbar
ID:102 View Protection:ATTENDEE Updated Time:2021-07-21 20:06:11 Hits:1346 Oral Presentation

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Abstract
This paper presents a SiC multichip power module with low parasitic inductance and symmetric layout of chips. The novelty of this module lies in the integration of a laminated busbar which can result in a significant reduction of the module parasitic inductance. Moreover, a 3D vertical structure design can reduce the commutation loop area inside the module, thereby further achieving a lower commutation loop inductance. Besides, a fan-shaped DBC layout is designed to ensure the symmetrical layout of the paralleled chips, which can realize a better current sharing performance. By the Ansys Q3D, the extracted parasitic inductance of the module is about 5.63nH, and the the imbalance degree between each parallel branch is about 5.8%. Finally, the low parasitic inductance and highly symmetry of the module are verified by the experimental tests.
Keywords
Low Parasitic Inductance,current sharing,Laminated Busbar,Symmetrical design
Speaker
Yuanjian Liu
HeFei University of Technology

Submission Author
Jianing Wang HeFei University of Technology;Institute of Energy,Hefei Comprehensive National Science Center
Yuanjian Liu HeFei University of Technology
Shaolin Yu HeFei University of Technology
Chen Wang HeFei University of Technology
Lijian Ding HeFei University of Technology
Nan Jiang Institute of Energy,Hefei Comprehensive National Science Center
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Important Date
  • Conference Date

    Aug 25

    2021

    to

    Aug 27

    2021

  • Apr 21 2021

    Abstract Submission Deadline

  • May 15 2021

    Abstract Notification of Acceptance

  • Jun 25 2021

    Final Paper Deadline

  • Aug 24 2021

    Contribution Submission Deadline

  • Aug 27 2021

    Registration deadline

Sponsored By
IEEE
IEEE ELECTRONIC DEVICE SOCIETY
Organized By
Huazhong University of Science and Technology