Multiple UIS Ruggedness of 1200V Asymmetric Trench SiC MOSFETs
ID:94 View Protection:ATTENDEE Updated Time:2021-08-18 20:38:44 Hits:1527 Oral Presentation

Start Time:2021-08-27 09:00(Asia/Shanghai)

Duration:15min

Session:Room2 Oral Session 2 » S5&S6WBG Device Design and Gate Drivers

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Abstract
In this paper, 1200 V asymmetric trench silicon carbide (SiC) metal–oxide–semiconductorfield-effect transistors (MOSFETs) are investigated by experiment under multiple unclamped inductive switching (UIS) events. The degradation degree of electrical characteristics and failure modes are evaluated under various avalanche energy ratio. Meanwhile, Focus Ion Beam (FIB) cut illustrates the cross-section of damage point. For low energy ratio condition, the increasing of Ron demonstrates that thermal fatigue is main root of failure. However, burn out of field oxide and metal Al is shown under high energy ratio.
Keywords
Failure mode,Asymmetric Trench,SiC MOSFET,Multiple UIS
Speaker
Wei Huang
University of Electronic Science and Technology of China

Submission Author
Jiayue Liu University of Electronic Science and Technology of China
Xiaochuan Deng University of Electronic Science and Technology of China
Xu Li University of Electronic Science and Technology of China
Wei Huang University of Electronic Science and Technology of China
ZhiQiang Li China Academy of Engineering Physics
Hongling Lu China Aerospace Science and Technology Corporation
Xuan Li University of Electronic Science and Technology of China
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Important Date
  • Conference Date

    Aug 25

    2021

    to

    Aug 27

    2021

  • Apr 21 2021

    Abstract Submission Deadline

  • May 15 2021

    Abstract Notification of Acceptance

  • Jun 25 2021

    Final Paper Deadline

  • Aug 24 2021

    Contribution Submission Deadline

  • Aug 27 2021

    Registration deadline

Sponsored By
IEEE
IEEE ELECTRONIC DEVICE SOCIETY
Organized By
Huazhong University of Science and Technology