Abstract List
My Submissions
58
Design and Analysis of Elementary Arithmetic Circuit for Clock Driven Reconfigurable Execution UnitFinal Paper

ChenNaijin *

#Session 6: IC设计与EDA II

55
基于机器学习的网表级时序预测方法Final Paper

贺旭*

#Session 6: IC设计与EDA II

45
RGCN：基于忆阻器的图卷积神经网络加速器设计Final Paper

午康俊*, LiBing*, wangjing*, GaoLan*, ZhangWeigong*

#Session 6: IC设计与EDA II

32
Reconfigurable Approximate Multiplication Architecture for CNN-Based Speech Recognition Using Wallace Tree Tensor Multiplier UnitFinal Paper

LiuBo *

#Session 6: IC设计与EDA II

16
Approximate C-elements: A Low Power TNU-Resilient LatchFinal Paper

HuangZhengfeng *

#Session 6: IC设计与EDA II

12
A High-Speed Quadruple-Node-Upset-Tolerant Latch in 22nm CMOS TechnologyFinal Paper

HuangZhengfeng *

#Session 6: IC设计与EDA II

    6 Records 1/1
Important Date

  • Conference Date

    Dec 11

    2021

    to

    Dec 12

    2021

  • Aug 18 2021

    Registration deadline

Sponsored By
中国计算机学会
Organized By
中国计算机学会容错计算专业委员会
同济大学软件学院
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