第十九届全国容错计算学术会议 (CFTC 2021)

With the growing complexity of integrated circuits (ICs), more and more test patterns (TP) are required so as to detect more defects. However, a large number of invalid patterns (pattern that can make the test pass) continues to increase test time (TT) and, consequently, Test Cost (TC) . Considering the problem that TT is too long and TC is increasing, this paper proposes an improved K-Nearest Neighbor (KNN) algorithm to select the valid patterns (pattern that can make the test fail) only. Experimental results demonstrate that the proposed method succeed in reducing 1.75 times TT compared with the traditional method with all patterns. In addition, the improved KNN algorithm aims at using the minimum number of TP to discover the maximum number of defects, which can reduce TT without increasing the number of defects obviously. Furthermore, the experimental results represent the optimal compromise between TC and test quality (TQ).

VLSI test;machine learning (ML);test patterns (TP);test cost (TC)