Analysis of the DC-link Capacitor Ripple Current for Neutral-Point-Clamped Three Level Inverter
ID:68 View Protection:ATTENDEE Updated Time:2023-11-21 19:52:34 Hits:1030 Oral Presentation

Start Time:2023-12-09 11:30(Asia/Shanghai)

Duration:15min

Session:S2 Power electronic technology and application » S2Power electronic technology and application

Presentation File

Tips: Only the registered participant can access the file. Please sign in first.

Abstract
This paper introduces 240-degree clamped pulse-width modulation strategy (240CPWM), traditional space vector modulation (SVPWM) and discontinuous pulse width modulation (DPWM1) for neutral-point-clamped three-level (NPC-3LI) inverters with a previa boost converter and provides a reasoned analysis of the capacitive ripple current with three PWM strategies and derives the calculation expressions. Using 240CPWM in inverters can greatly reduce switching losses, especially at a power factor of 1, which reduces switching losses by 85% and has nearly equal total harmonic distortion (THD) compared to SVPWM. In comparison, using 240-degree clamped pulse width modulation strategy can reduce the value of capacitive ripple current at full power factor, especially at high power factor, which will help reduce the volume on the DC side support capacitor.
Keywords
neutral-point-clamped;PWM;three-level inverters;ripple
Speaker
Xiaosa Sui
student Shanghai University

Submission Author
Xiaosa Sui Shanghai University
Deliang Wu Shanghai University
Submit Comment
Verify Code Change Another
All Comments
Important Date
  • Conference Date

    Dec 08

    2023

    to

    Dec 10

    2023

  • Nov 01 2023

    Draft paper submission deadline

  • Dec 10 2023

    Registration deadline

Sponsored By
IEEE IAS
Organized By
Southwest Jiaotong University (SWJTU)