2014 IEEE Global High Tech Congress on Electronics (GHTCE 2014)

180 / 1971-01-01 00:00:00

Novel Implementation Of Mmse-based Mimo Detector On Fpga

MMSE,MIMO Detector,MGS,QR Decomposition,FPGA

Multiple-input multiple-output (MIMO) technology significantly improves the performance of wireless communication system, but it also increases the complexity of detector largely, especially in combination with orthogonal frequency division multiplexing (OFDM) technology. In this paper, we propose minimum mean square error (MMSE) detector on FPGA based on modified Gram-Schmidt QR decomposition (MGS-QRD) algorithm. Several optimization schemes, such as data-level
parallelism, task-level parallelism and module reuse strategies,are used to enhance the detecting throughput. We implement the detector on Xilinx Virtex6 FPGA devices, and achieve 55.75 MInv/s and maximum 0.88us latency with 223 MHz clock for 4 × 4 MIMO system, which meets the demands for real-time detecting in MIMO-OFDM systems and is superior to other implementations to date.