IEEE 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET 2016)

233 / 2016-01-21 17:44:27

Mapping of Five input Wallace tree Using Cadence Tool for Low Power, Low area and High Speed

High-Level synthesis, Wallace tree algorithm, carry save adder, area, low power, delay, DSP, VLSI.

Now a days, low power Very Large Scale Integration (VLSI) circuit plays an important role in designing efficient energy saving electronic systems for high speed performance. In this, low power consumption is one of the most important criteria in various devices like mobile phones, laptops, high speed work stations etc., Due to the integration of many components on the VLSI circuit designs, power consumption is getting increased. Over a period, power management has become a major issue and challenging task for improving the battery life time and reducing the charging time in the electronic handheld devices. This paper presents five input Wallace tree and carry save adder are mapped into Cadence Encounter(R) RTL Compiler Version v14.20-s013_1.By efficiently mapping into cadence tool, area, power and delay are decreased. The results of mapping are viewed using RTL synthesis tool in cadence VIRTUOSO at 180 nm technology and 1.8V. Based on DSP architectures, the code for low power is generated using five input Wallace tree and carry save adder.