2017 IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET 2017)

217 / 2017-01-12 19:46:56

Distributed Arithmetic Architectures for FIR Filters -A Comparative review

Distributed Arithmetic, LUT, FIR Filter, OBC, Reconfigurable FIR filter, systolic DA

Finite impulse response (FIR) filter is an influential block in various signal processing applications. The complexities in VLSI implementation of FIR filters is dominated by the number of multiply and accumulate (MAC) operations. Distributed Arithmetic (DA) is an alternative technique where the MAC operations can be replaced by a series of look-up tables and addition operations. FIR filter based on DA are computationally efficient because of the high degree of mechanization involved in the implementation of MAC operations using DA. This paper reviews the existing FIR filter architectures based on DA. Many reconfigurable and non-reconfigurable FIR filter architectures are presented. LUT based DA and LUT-less DA are the significant methods in the implementation of non-reconfigurable filters. This brief summarizes the area and power reports of the existing non-reconfigurable FIR filter architectures based on both LUT based DA and LUT-less DA. One dimensional and two dimensional systolic DA based architectures for FIR filter implementation are also briefed. shared LUT reconfigurable FIR filters fall under reconfigurable DA architectures. This paper presents the comparative results of reconfigurable FIR filter architectures in terms power delay product, area-delay product, minimum sampling period and maximum sampling frequency. This survey can form a basis for further research on DA based FIR filter architectures.