2017 IEEE International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET 2017)

265 / 2017-01-25 16:49:39

Design and Implementation of Low Power Test Pattern Generator Using Low Transitions LFSR

12636,12637,12638,12639,12640

The Low transition Test Pattern Generation is a very crucial technique for testing of a complex architecture of VLSI design. In this paper, 32-bit test pattern generator has been proposed for testing the VLSI design. This 32-bit test pattern generator is implemented with efficient LFSR and with extra combinational circuitry which achieved Low power consumption. This paper is implemented using Xilinx 13.1 ISE design suite in Verilog HDL. The switching activities between the tests vectors are reduced this result in low power consumption. The design of test pattern generation which yield a power of 35 mw with a latency of 5.194ns. The switching activity required for 32-bit test pattern generation has been improved and presented in this paper.