2017 Eleventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS)

NoC Architecture and Implementation

• Network architecture (topology, routing, arbitration)
• NoC Quality of Service
• Timing, synchronous/asynchronous communication
• NoC reliability issues
• Network interface issues
• NoC design methodologies and tools
• Signaling and circuit design for NoC links

NoC Application

• Mapping of applications onto NoCs
• NoC case studies, application-specific NoC design
• NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
• NoC designs for heterogeneous systems, fused CPU-GPU architectures, FPGA-based systems, etc
• Scalable modeling of NoCs

Novel NoC Technologies

• New physical interconnect technologies, e.g., carbon nanotubes, wireless NoCs, through-silicon, etc.
• NoCs for 3D and 2.5D packages
• Package-specific NoC design
• Optical, RF, & emerging technologies for on-chip/in-package interconnects
• In-memory network and NoCs for new memory technologies

NoC at the Un-Core and System-level

• Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols in NoCs
• NoC support for memory and cache access
• OS support for NoCs
• Programming models including shared memory, message passing, and novel programming models
• Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks

NoC Analysis and Verification

• Power, energy and thermal issues (at the NoC, un-core and/or system-level)
• Benchmarking & experience with NoC-based hardware
• Modeling, simulation, and synthesis of NoCs
• Verification, debug, and test of NoCs
• Metrics and benchmarks for NoCs

On-Chip Communication Optimization

• Communication efficient algorithms
• Communication workload characterization and evaluation
• Energy efficient NoCs and energy minimization

Off-Chip and Rack-Level Communication

• All aspects of inter-chip network design
• All aspects of rack-level network design