Introduction
International Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems—covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process and design improvement. At ITC, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. This ITC conference will be focusing on Test technology development in Asia and India but the submissions may not be limited to topics related to this region. Topics related to DFT and test development across multi geographical regions will be of special interest.
ITC (India) conference is being held in India under the International Test conference banner to invite researchers, industry teams to present their development work which has a focus on ASIA. This includes design teams which have multiple national presences and are developing designs and products across multiple sites across the world. ITC India 2017 is Technically Co-sponsored by IEEE Bangalore Section.
Call for paper
Important date
Submission Topics
ITC India invites submissions on the latest advances in test, validation and diagnosis of ICs, boards and systems.
Topics of interest include (not limited to):
- 3D/2.5D Test
- Adaptive Test in Practice
- ATE/Probe Card Design
- Advances in Boundary Scan
- Bring Up
- Data Driven Methods
- Data Exchange and Infrastructure
- Defect-Oriented Testing
- DFM and Test Diagnosis
- Economics of Test
- End-to-End Data Analysis
- Embedded BIST & DFT
- Emerging Defect Mechanisms
- Hardware Security and Trust
- IoT Testing
- Jitter, High-Speed I/O and RF Test
- Known-Good-Die testing
- Memory Test and Repair
- MEMS Testing
- Mixed-Signal and Analog Test
- New Technologies and Test
- On-Chip Test Compression
- Online Test
- Pre- and Post- Silicon Validation
- Power Issues in Test
- Protocol-aware Test
- Reliability and Resilience
- Scan Based Test
- SoC/SiP/NoC Test
- Silicon Debug
- Simulation and Test
- System Test (Applications)
- System Test (Hardware/Software)
- Test-to-Design Feedback
- Test Escape Analysis
- Test Flow Optimizations
- Test Generation and Validation
- Test Resource Partitioning
- Test Standards
- Test Time Analysis and Reduction
- Testing High Speed Optics/Photonics
- Timing Test
- Yield Analysis and Optimization
All Comments
Important Date
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Conference Date
Jul 09
2017
toJul 11
2017
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May 05 2017
Abstract Submission Deadline
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May 05 2017
Draft paper submission deadline
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Jun 02 2017
Draft Paper Acceptance Notification
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Jun 16 2017
Final Paper Deadline
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Jul 11 2017
Registration deadline
Sponsored By
Contact Information
- S. Sivanantham
- ss******@ieee.org
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