Introduction

EPEPS is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs. EPEPS is sponsored by the IEEE Components, Packaging and Manufacturing Technology Society.

Call for paper

Important date

2017-06-30
Draft paper submission deadline

with emphasis on:

  • System-level, board-level and on-chip interconnects
  • High-speed channels, links, backplanes, serial and parallel interconnects, SerDes
  • Low power mobile and personal applications
  • Multiconductor transmission lines
  • Memory and DDR interfaces
  • Jitter and noise management
  • Signal and thermal integrity
  • Power integrity and power distribution networks (PDNs)
  • Electronic packages and microsystems
  • 3D interconnects, 3D packages, TSVs and MCMs
  • Nano interconnects and nano structures
  • RF/microwave packaging structures, RFICs, mixed signal modules and wireless switches
  • Package-chip co-design
  • Electromagnetic (EM) and EM interference modeling, simulation algorithms, tools and flows
  • Macromodeling and model order reduction as it applies to electrical analysis
  • Advanced and parallel CAD techniques for signal, power and thermal integrity analysis
  • Measurement and data analysis techniques for system-level and on-chip structures.
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Important Date

  • Conference Date

    Oct 15

    2017

    to

    Oct 18

    2017

  • Jun 30 2017

    Draft paper submission deadline

  • Oct 18 2017

    Registration deadline

Sponsored By
IEEE
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