Introduction

The IEEE Latin-American Test Symposium (LATS, previously Latin-American Test Workshop - LATW) is a recognized forum for test and fault tolerance professionals and technologists from all over the world, in particular from Latin America, to present and discuss various aspects of system, board, and component testing and fault-tolerance with design, manufacturing and field considerations in mind. Presented papers are also published in the IEEE Xplore Digital Library. The best papers of the 19th LATS will be invited to re-submit to IEEE Design & Test,Journal of Electronic Testing: Theory and Applications - JETTA (Springer), Journal of Low Power Electronics - JOLPE (American Scientific Publishers), and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).

Located in the southeast region of Brazil, São Paulo is an alpha global city and is the most populous city in Brazil as well as in the Southern Hemisphere. It exerts strong international influences in commerce, finance, arts and entertainment. With a GDP of US$477 billions, the São Paulo city alone could be ranked 24th globally compared with countries. (2016 Estimates). The metropolis is also home to several of the tallest skyscraper buildings in Brazil, having cultural, economic and political influence both nationally and internationally. It is home to monuments, parks and museums such as the Latin American Memorial, the Ibirapuera Park, Museum of Ipiranga, Sao Paulo Museum of Art, and the Museum of the Portuguese Language. In 2016, lived in the city native inhabitants from 196 different countries. According to a report from 2011, São Paulo was expected to have the third highest economic growth in the world between 2011 and 2025, after London and Mexico City.

Call for paper

Important date

2017-11-25
Abstract submission deadline
2017-12-09
Draft paper submission deadline
2018-01-13
Draft paper acceptance notification
2018-01-20
Final paper submission deadline

Submission Topics

  • Analog Mixed Signal Test 

  • Automatic Test Generation 

  • Built-In Self-Test 

  • Defect-Based Test 

  • Design and Synthesis for Testability 

  • Design for Electromagnetic Compatibility 

  • Design for Reliable Embedded Software 

  • Design Verification/Validation 

  • Economics of Test 

  • Fault Analysis and Diagnosis 

  • Fault Modeling and Simulation 

  • Fault-Tolerance in HW/SW 

  • Fault-Tolerant Architectures 

  • Hardening Techniques 

  • Hardware Security 

  • Memory Test and Repair 

  • On-Line Testing 

  • Process Control and Measurements 

  • Radiation/EMI 

  • Software Fault-Tolerance 

  • Software On-Line Testing 

  • System-on-Chip Test 

  • Test Resource Partitioning 

  • Yield Optimization 

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Important Date
  • Conference Date

    Mar 13

    2018

    to

    Mar 16

    2018

  • Nov 25 2017

    Abstract Submission Deadline

  • Dec 09 2017

    Draft paper submission deadline

  • Jan 13 2018

    Draft Paper Acceptance Notification

  • Jan 20 2018

    Final Paper Deadline

  • Mar 16 2018

    Registration deadline