Abstract Details
645 / 2019-03-24 11:35:18
A Novel Highly Reliable 12T SRAM Bitcell Design
Highly reliable SRAM, bitcell design, dual port bitcell, soft error, single event upset (SEU), RSNM
Final Paper
This paper presents a novel highly reliable dual port 12T static random access memory (SRAM) bitcell. Compared with the state-of-the-art soft-error-tolerant bitcells and the traditional 6T, the proposed 12T exhibits much larger read noise margin (RSNM), and also saves 85.4% read access time on average, making it much suitable for high-speed highly reliable applications.
Important Date
-
Conference Date
Jun 12
2019
toJun 14
2019
-
Jun 12 2019
Draft paper submission deadline
-
Jun 14 2019
Registration deadline
Organized By
Xi'an University of Technology
Contact Information
- Dr. Zhaonian Yang
- ed******@126.com
- 177********
Previous Conferences
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2025-06-06 China Yinchuan
2025 IEEE International Conference on Electron Devices and Solid-State Circuits -
2017-10-18 Taiwan, China
2017 International Conference on Electron Devices and Solid-State Circuits -
2016-08-03 Hong Kong, China Hongkong，China
2016 IEEE International Conference on Electron Devices and Solid-State Circuits -
2015-06-01 Singapore
2015 IEEE International Conference on Electron Devices and Solid-State Circuits
