Abstract Details
  1. Home
  2. Abstract List
  3. Abstract Details
651 / 2019-04-02 18:43:21
Enhanced LVTSCR with High Holding Voltage in Advanced CMOS technology
Electrostatic discharge (ESD),LVTSCR,holding voltage,latch-up immunity
Plenary track > Device and Circuit Reliability
Final Paper
Meichen Huang / University of Electronic Science and Technology of China
Feibo Du / University of Electronic Science and Technology of China
Fei Hou / University of Electronic Science and Technology of China
Wenqiang Song / University of Electronic Science and Technology of China
Jizhi Liu / University of Electronic Science and Technology of China
Zhiwei Liu / University of Electronic Science and Technology of China
In this paper, an improved low voltage triggered silicon-controlled rectifier (LVTSCR) for electrostatic discharge protection is proposed. By carefully optimizing the electric field distribution at the junction of P-WELL and N-WELL in LVTSCR，the holding voltage of the enhanced LVTSCR (ELVTSCR) can be effectively increased to improve latch-up immunity. TCAD simulation indicates that compared with traditional LVTSCR, the proposed ELVTSCR has higher and adjustable holding voltage as well as comparable trigger voltage, making it suitable to provide ESD solutions for high voltage (HV) applications in advanced CMOS technology.
Important Date

  • Conference Date

    Jun 12

    2019

    to

    Jun 14

    2019

  • Jun 12 2019

    Draft paper submission deadline

  • Jun 14 2019

    Registration deadline

Organized By
Xi'an University of Technology
Contact Information
Login to view full contact details
Previous Conferences