Scan Test Escapes, New Fault Models, and the Effectiveness of Functional System Level Tests
ID:1 View Protection:PUBLIC Updated Time:2021-08-11 11:19:51 Hits:845 Tutorial

Start Time:2021-08-18 19:00(Asia/Shanghai)

Duration:180min

Session:TS Tutorial » TS2Tutorial 2, Scan Test Escapes, New Fault Models, and the Effectiveness of Functional System Level Tests

Abstract
This tutorial aims at understanding the increasing use of functional system level tests (SLTs) as an additional final defect screen before processor SOCs are shipped for assembly. For this, we take an in-depth look at traditional scan based Stuck-at and TDF tests to understand potential sources of test escapes. We also extensively discuss the effectiveness of new test generation methodologies such as Cell Aware, Gate Exhaustive, Transistor Stuck-Open, and Timing Aware in plugging these structural test holes. Based on this, we identify failures that can still remain undetected by low cost scan structural tests, and require the use of expensive functional SLTs to achieve desired defect levels. In conclusion, we suggest strategies to minimize use SLTs without impacting defect levels.
Keywords
3LPP coating
Speaker
Adit Singh
Auburn University

Dr. Adit Singh is Godbold Endowed Chair Professor of Electrical and Computer Engineering at Auburn University, where he has served on the faculty since 1991. Earlier he has held faculty positions at the University of Massachusetts in Amherst, and Virginia Tech, in Blacksburg. He has also held visiting professorships at the University of Freiburg, Germany, and the University of Tokyo, Japan, and a Fulbright at the University Polytechnic of Catalonia in Barcelona, Spain. His research interests span all aspects of VLSI technology, with an emphasis on IC test and reliability; he has published widely in these areas. Professor Singh has held leadership roles as General Chair/Co-Chair/Program Chair for dozens of VLSI design and test conferences, and regularly serves on the Steering and Program Committees of many major international conferences in test and design automation. For two terms (2007-11), he was elected Chair of the IEEE Test Technology Technical Council (TTTC), and also served (2011-2015) on the Board of Governors of the IEEE Council on Design Automation (CEDA). He holds a B.Tech in Electrical Engineering from IIT Kanpur, and the M.S. and Ph.D. from Virginia Tech. He was elected Fellow of IEEE in 2002.

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Important Date
  • Conference Date

    Aug 18

    2021

    to

    Aug 20

    2021

  • May 10 2021

    Draft paper submission deadline

  • Aug 16 2021

    Early Bird Registration

  • Aug 19 2021

    Contribution Submission Deadline

  • Aug 20 2021

    Registration deadline

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