Characterization, Modeling and Test of SyntheticAnti-FerromagnetFlip Defect in STT-MRAMs
ID:49 View Protection:PUBLIC Updated Time:2021-08-15 22:53:33 Hits:650 Invited speech

Start Time:2021-08-20 21:05(Asia/Shanghai)

Duration:20min

Session:SS Special Session » SS5B6 Top Papers of ITC’2020

Abstract
Understanding the manufacturing defects in magnetic tunnel junctions (MTJs), which are the data-storing elements in STT-MRAMs, and their resultant faulty behaviors are crucial for developing high-quality test solutions. This paper introduces a new type of MTJ defect: synthetic anti-ferromagnet flip (SAFF) defect, wherein the magnetization in both the hard layer and reference layer of MTJ devices undergoes an unintended flip to the opposite direction. Both magnetic and electrical measurement data of SAFF defect in fabricated MTJ devices is presented; it shows that such a defect reverses the polarity of stray field at the free layer of MTJ, while it has no electrical impact on the single isolated device. The paper also demonstrates that using the conventional fault modeling and test approach fails to appropriately model and test such a defect. Therefore device-aware fault modeling and test approach is used. It first physically models the defect and incorporate it into a Verilog-A MTJ compact model, which is afterwards calibrated with silicon data. The model is thereafter used for fault analysis and modeling within an STT-MRAM array; simulation results show that a SAFF defect may lead to a transient passive neighborhood pattern sensitive fault (tPNPSF) when all neighboring cells are in logic ‘1’ state. Finally, test solutions for such fault are discussed.
Keywords
Device-aware test,;STT-MRAM;Manufacturing defects,;Fault models;Memory test
Speaker
Lizhou Wu
Post Doc. Delft University of Technology

Lizhou Wu received the BSc degree in electronic science and engineering from Nanjing University and the PhD degree with honors from Delft University of Technology. 

His research interests cover two domains: 1) Spintronic design, design automation, and test, 2) emerging computing paradigms based on non-volatile memory devices. He has (co-)authored 15 ACM/IEEE conference and journal papers. He is the recipients of best paper award at DATE'20, distinguished paper at ITC'20, best paper award nomination at ETS'19 and DATE'21.

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    Aug 18

    2021

    to

    Aug 20

    2021

  • May 10 2021

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  • Aug 16 2021

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