2021 IEEE International Test Conference in Asia (ITC-Asia 2021)

System level tests (SLTs) are important and expensive procedures to ensure high IC quality. In volumen production stage with stable high yields, efforts such as random sampling have been used to improve testing efficiency. However random sampling doesn't fully utilize information gathered before SLT and is not optimal. In this paper we propose both supervised  (SVM) and unsupervised (AutoEncoder) machine learning algorithms to predict or estimate SLT failures based on earlier stage Final Test (FT) test data and further use the estimated pseudo probabilities to guide the selection of dies for system level testing. Experiments on a real product dataset, consisting of 158 wafers, each with 3118 FT testing variables reveal robustness of the models. Through the gains chart of the models, we provide a flexible smart sampling strategy and demonstrate its potential of reducing SLT testing cost by 40% with minor impact on Defective Parts Per Million(DPPM). Our cases also show that such smart sampling approach is very well suited for engaging adaptive test flow optimization achieving balanced goals of improving test effeciency, reducing cost and ensuring high product quality at the same time.

DPPM, SLT, Smart Sampling, SVM, AutoEncoder, Machine Learning