2021 IEEE International Test Conference in Asia (ITC-Asia 2021)

This paper presents a synthesizable 50% Duty-Cycle Monitor (DCM) supporting a wide range of clock frequency from 100MHz to 1.2GHz, using in a 90nm CMOS process. We demonstrate that a wide frequency range and a high resolution can be achieved by only standard cells with a reasonable amount of area overhead. Such a design can be easily used as an off-the-shelf IP to check the duty-cycle of a clock signal that should remain at 50% at all times when used in a Double- Data-Rate (DDR) application that captures data at both the rising and the falling clock edges. In our design, a feature – called clock frequency adjustment scheme – is developed to achieve robustness in various process and environmental conditions. The benefit of using such a monitor is that an alarm of performance hazard can be raised whenever there is an excessive Duty-Cycle Error on a DDR clock signal.

Duty-Cycle;Duty-Cycle Monitor;Double Data Rate;Synthesizable Design;Wide Range