An SRAM Test Quality Improvement Method For Automotive chips
ID:59 View Protection:ATTENDEE Updated Time:2021-08-24 20:47:32 Hits:667 Oral Presentation

Start Time:2021-08-20 20:00(Asia/Shanghai)

Duration:20min

Session:IS Industrial Session » IS4B5. Industry Practice in SoC and Memory Test

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Abstract
Automotive chips have high requirements on chip test quality. The degree of defects covered by the SRAM test algorithm directly determines the test quality of SRAM. With the evolution of IC manufacturing technology, the defect modeling of SRAM becomes more and more complicated. How to establish a complete test algorithm has become a challenge in the industry. Currently, the industry develops a new test algorithm by establishing defect models on the advanced process nodes. However, the defect model is different from the defect in the actual process. The mass production test shows that many chips are in the critical defect state and cannot be detected. In this paper, we propose an improved memory defect analysis method, and develop a novel defect and test scheme. The mass production test results show that this test scheme can detect the critical defect chips effectively.
 
Keywords
MBIST, test algorithm, dynamic faults, defect simulation,automotive
Speaker
Tuanhui Xu
employees

Tuanhui xu is a senior DFT engineer at HiSilicon Semiconductor. He is responsible for researching memory defects and memory fault models, developing test algorithms, and analyzing faulty chips. He received a bachelor's degree in electronic information engineering from Xi'an Electronic University in 2006, and a master's degree in computer science from China Electronic Technology Group in 2010. He joined HiSilicon Semiconductor Corporation in 2011 and engaged in DFT-related work.
 

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    2021

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