Rigorous Test Flow for PLL to Identify Weak Devices
ID:65 View Protection:ATTENDEE Updated Time:2021-08-18 20:53:04 Hits:765 Oral Presentation

Start Time:2021-08-20 21:45(Asia/Shanghai)

Duration:20min

Session:SS Special Session » SS4A6. Test Methods Towards Zero Failure Rate for Safety-Critical ICs

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Abstract
Presenter: Prof. Shi-Yu Huang, National Tsing Hua University, Taiwan
Education:
BS, EE Dept., National Taiwan University, 1988
MS, EE Dept., National Taiwan University, 1992
Ph.D., ECE Dept., Univ. of Santa Barbara, 1997
Experience:
Joined National Tsing Hua University since 1999
Current Research Interests:
Cell-based Timing Circuit Design and Compiler,
and their applications for VLSI Testing and Online Monitoring.
 
Keywords
Speaker
Shi-Yu Huang
National Tsing Hua University

Presenter: Prof. Shi-Yu Huang, National Tsing Hua University, Taiwan
Education:
BS, EE Dept., National Taiwan University, 1988
MS, EE Dept., National Taiwan University, 1992
Ph.D., ECE Dept., Univ. of Santa Barbara, 1997
Experience:
Joined National Tsing Hua University since 1999
Current Research Interests:
Cell-based Timing Circuit Design and Compiler,
and their applications for VLSI Testing and Online Monitoring.

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    2021

    to

    Aug 20

    2021

  • May 10 2021

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  • Aug 16 2021

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