Integrated Scratch Marker for Wafer Defect Diagnosis
ID:69 View Protection:ATTENDEE Updated Time:2021-08-23 14:35:52 Hits:965 Oral Presentation

Start Time:2021-08-20 21:25(Asia/Shanghai)

Duration:20min

Session:SS Special Session » SS4A6. Test Methods Towards Zero Failure Rate for Safety-Critical ICs

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Abstract
The scratch defect type is difficult to recognize because the position, shape, size and curvature vary widely from one scratch to another. Discontinuity points within scratches also contribute to the low recognition rate, and such points are often hidden defective dies that become reliability threat. The recognition rate for scratches is among the lowest in all patterns even if the overall accuracy is high. In this paper, we propose a novel scratch pattern recognition method.
The method is validated by real products. Experimental results show that the average recall, precision and accuracy achieved by the proposed method are 97.22%, 98.81%, and 99.92%, respectively. Furthermore, the proposed method is based on image processing techniques alone with low processing time. In contrast to machine-learning based methods, there is no need to train a complicated prediction model.
Keywords
scratch defect;wafer map;wafer test
Speaker
Katherine Shu-Min Li
National Sun Yat-sen University

Katherine Shu-Min Li (S’04, M’06, S. M' 13-now) received the B.S. degree from Rutgers University, New Brunswick, NJ, and the M.S. and Ph.D. degrees from National Chiao  Tung University,  Hsinchu,  Taiwan, in 2001 and 2006, respectively. She is currently a Full Professor with the Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan.
Her current  research  interests  include  Interposer Test, 2.5D/3D/SiP IC Test, Microfluidic Chip Synthesis & Test, Hardware Security & Trojan, Side Channel Effect, Design for Security (DfS), Machine Learning, Big Data, Crosstalk  Effects,  Signal & Power Integrity, SOC testing, Floorplanning and Routing for Testability and Yield Enhancement, Design for Yield (DfX), Scan  Reordering, Scan  Routing,  Low-Power  Scan  Techniques, particularly on Oscillation Ring Test Schemes, and Interconnect Optimization. Her recent researches involve also in cross-field exploration in research field of IC Design & Test (D&T), Electronics Design Automation & Test (EDA&T), Computer Integrated Manufacturing (CIM), Computer Aided Design (CAD) and Computer Aided Engineering (CAE) in Factory Automation (Industry 4.0), especially High Frequency Trading (HFT) in FinTech.
Dr.  Li  is  a  member  of  IEEE Education and IEEE  Circuits   and  Systems Society, Association for Computing Machinery (ACM), and ACM Special Interest Group on Design Automation, IEEE Women in Engineering (WIE) (Oct. 13-now).

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Important Date
  • Conference Date

    Aug 18

    2021

    to

    Aug 20

    2021

  • May 10 2021

    Draft paper submission deadline

  • Aug 16 2021

    Early Bird Registration

  • Aug 19 2021

    Contribution Submission Deadline

  • Aug 20 2021

    Registration deadline

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Tongji University
Chinese Computer Federation
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