Requirements of high-speed scan and DFT implementation
ID:71 View Protection:ATTENDEE Updated Time:2021-08-19 19:29:32 Hits:813 Oral Presentation

Start Time:2021-08-19 21:05(Asia/Shanghai)

Duration:20min

Session:IS Industrial Session » IS1B2. The Advancement of 1149.10

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Abstract
Compared chip scale increasing exponentially with Moore’s law, Scan IO bandwidth keeps stable. Using a serial high-speed interface to load-unload Scan data is a very effective solution to replace the traditional one which would make higher scan test parallelism, more reasonable Channel Compression and reduced Test System complexly.
From a semiconductor company, the presentation would introduce some industrial implementation trends or requirement to HSPHY design, Physical design, SCAN Compression and vector convert.   
The Standard’s application would be begin with Scan Data throughput to end with Test Data throughput containing Scan data, JTAG data or other data. In the end of the presentation, there is some prospective to the future of High-speed Scan technology.
Keywords
High Speed SCAN;;Scan distrubution system;PCS;PHY
Speaker
Fu Haitao
DFT technical expert HISILICON

Fu haitao received the B.S and M.S degree in University of Electronic Science and Technology of China, Chengdu, China, in 2007 and 2010, respectively.
In 2010, he joined Hisilicon Corporation. Now he is currently a director managing DFT technology & Solution team. His current research interests include High-speed SCAN or JTAG architecture, mixed-signal structural testing.
 

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Important Date
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    Aug 18

    2021

    to

    Aug 20

    2021

  • May 10 2021

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  • Aug 16 2021

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