3rd IEEE International Workshop on Test and Validation of High Speed Analog Circuits

Demand for higher bandwidths never lets up in the world of communication and networks. While we struggle today to make 40Gbps line-rates a reality, plans are already afoot for 400Gbps. Similarly in wireless communications, 60Ghz is coming on-line today, but designers are already planning the next few generations up to Thz. What is high-speed? It clearly depends: on the medium of transmission, on power constraints, on process technology, on link parallelism, on cost and quality requirements and on the electrical and thermal environment of operation. These constraints define a multi-dimensional box that designers are placed in and asked to provide the highest bandwidth they can, inside a room whose walls seem constantly to move inwards. A lot of the functionality is increasingly analog with strict standards regulating their design and use. And it is a race with no end in sight. The IEEE Workshop on Test and Validation of High Speed Analog Circuits is designed to address a big aspect of this race: cost and quality. Increasing speed has given rise to a spike in complexity of analog circuits. This has been further stressed by the need for integrating with digital functionality in SOCs. Whether embedding in monolithic dice or integrating in a SiP, integration has thrown its share of problems. Defect coverage alone is no longer sufficient to qualify a die. We need parametric coverage, as early in the manufacturing flow, as possible. This workshop addresses defect and parametric coverage of all analog circuits involved in making high bandwidth communications a reality.