Introduction

Multicore systems are dominating the processor market ranging from embedded to high-performance systems. Processor manufactures have emphasized multi-core CPUs as the answer to scaling system performance. The core count increases with each chip multiprocessor generations due to the transistor node shrinks. To take advantage of current multicores, efficient load balancing and scheduling policies or strategies are required. In addition, it remains a challenge to identify and productively program applications for these systems with a resulting substantial performance improvement. A recent trend proposes heterogeneous systems as efficient processors to deal with performance and power. Different heterogeneity design choices have been explored, like hybrid CPU/GPU architectures that deal with parallel performance or systems with different core types implementing distinct InstructionSet Architectures (ISA). Finally, most real-time embedded applications are requiring high-performance computing and multicore/multithreaded/heterogeneous processors are becoming the common design choice. The aim of this workshop is to provide a forum for engineers and scientists to address the resulting challenge and to present new ideas, applications, and experience on all aspects of multicore/multithreaded/heterogeneous systems.

Call for paper

Important date

2015-05-31
Draft paper submission deadline
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Important Date
  • Conference Date

    Aug 24

    2015

    to

    Aug 26

    2015

  • May 31 2015

    Draft paper submission deadline

  • Aug 26 2015

    Registration deadline

Sponsored By
IEEE Computer Society
IEEE Technical Committee on Scalable Computing (TCSC)
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