Introduction

In order to further increase audience and scientific impact, the two sister conferences ULIS and EUROSOI have decided to merge in 2015 and the first joint EUROSOI-ULIS event was a sucess. The aim of the EUROSOI-ULIS Conference is to provide an open forum for the presentation and discussion of recent research in technology, physics, modeling, simulation and characterization of advanced nanoscale semiconductor-on-insulator and silicon-compatible devices. Papers corresponding to the More Moore, More than Moore and Beyond CMOS domains (alternative semiconductor and dielectric materials, innovative devices, circuit and system design, etc) are highly encouraged.

Call for paper

Important date

2015-11-02
Abstract submission deadline
2015-11-16
Draft paper acceptance notification
2016-01-18
Final paper submission deadline

Submission Topics

Topics include, but are not limited to

  • Advanced SOI materials and wafers

  • New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other 2D materials

  • Properties of ultra-thin films and buried oxides, defects, interface quality

  • Thin gate dielectrics: high-k materials for switches and memory

  • Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory (DRAM, Non-Volatile, SRAM, ReRAM...) applications

  • Physics mechanisms and innovative SOI-like devices

  • Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and tunnel FET structures, MEMS/NEMS, Beyond-CMOS nanodevices

  • New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain for Sensing, Energy harvesting, RF, High voltage, Imagers, Electronic cooling, etc.

  • CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling

  • Three-dimensional integration of devices and circuits, heterogeneous integration

  • Transport phenomena, compact modeling, device simulation, front- and back-end fabrication process simulation

  • Advanced test structures and characterization techniques, parameter extraction, reliability and variability issues for new materials and novel devices

Submit Comment
Verify Code Change Another
All Comments
Important Date
  • Conference Date

    Jan 25

    2016

    to

    Jan 27

    2016

  • Nov 02 2015

    Abstract Submission Deadline

  • Nov 16 2015

    Draft Paper Acceptance Notification

  • Jan 18 2016

    Final Paper Deadline

  • Jan 27 2016

    Registration deadline

Sponsored By
IEEE