2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)

Advanced Packaging: Flip-chip and wire-bond packaging, embedded passives and actives on substrates, 3D System in Packaging, etc.

TSV/Wafer Level Packaging: Wafer level packaging ( Fan in / Fan out ), embedded chip packaging, 2.5D/3D integration, TSV, Silicon & Glass interposer, RDL, bumping technologies, etc.

Interconnection Technologies: Au/Ag/Cu/Al Wire-bond / Wedge bond technology, Flip-chip & Cu pillar technology, solder alternatives (ICP, ACP, ACF, NCP, ICA), Cu to Cu, Wafer level bonding & die attachment (Pb-free) etc.

Emerging Technologies: Packaging technologies for MEMS, biomedical, optoelectronics, Internet of things, photo voltaic, printed electronics, wearable electronics, Photonics, LED, etc.

Materials and Substrates/Leadframes: Including all that polymer and solder materials, and Substrates / Interposer / Leadframes / PCB etc.

Processes and Automation/Equipments: new process development as well as equipment automation development.

Electrical Modeling & Simulations: Power plane modeling, signal integrity analysis of substrate/package.

Mechanical Modeling & Simulations: Thermo-mechanical, moisture, fracture, fatigue, vibration, Shock and drop impact modeling, Chip-package interaction, etc.

Thermal Characterization & Cooling Solutions: Thermal modeling and simulation, component, system and product level thermal management and characterization

Quality & Reliability: Component, board, system and product level reliability assessment, Interfacial adhesion, accelerated testing, failure characterization, etc.

Wafer/Package level & TSV Testing and Characterization: High-speed test architectures and systems design, 2.5D & 3D test methodologies, probe card design, package-test interaction, high-throughput