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Introduction

The last decade has seen significant changes in processor architectures to improve computing performances and to overcome the physical limitations of increasing the clock frequency.

This allowed processors to still scale according to Moore's law. However, a new challenge is becoming relevant today: The ever increasing power and energy requirements for operating the latest generation of HPC systems are key factors in limiting the peek performances of newer HPC systems and might make Exascale computing unsustainable for both technical and economic reasons. 

A possible solution is to find disruptive technologies in terms of new hardware architectures and energy aware system software which maximize the performance of HPC systems within a given power or energy budget. 

For example, accelerators -- like GPUs, co-Processors, FPGAs -- and many-core low-power SoCs address this issue using different strategies.

The use of these is becoming more and more relevant in high performance computing. A challenge is a proper system design in order to be able to optimize the energy to solution and the time to solution for all applications running on the HPC system. Additionally, the interaction between the data center cooling infrastructure, the HPC system, the HPC system software -- including but not limited to scheduling systems, compilers, and run-time tools - and the running applications, have a great impact on the final power and energy efficiency of current and future HPC systems. 

The workshop aims to strongly encourage the exchange of experiences and knowledge in novel solutions for improving the power and energy efficiency of HPC systems, and their application in HPC data centers. It focuses on analyzing and assessing new trends for high performance architecture, accelerators, and related changes in application algorithm design able to minimize the power and energy requirements for current and future HPC systems. Additionally, the workshop will look at challenges and tools for integrating the new generation HPC systems with the data centers for improved power and energy efficiency. 

Call for paper

Submission Topics

The WEHA Workshop topics include (but are not limited to) the following:

  • New Energy-aware Hardware Design

  • Algorithms and hardware architectures for reduced power, energy and heat

  • Power Prediction and Consumption Models and Monitoring Tools

  • Distributed infrastructures for collecting energy data and relevant context information

  • Accelerated Computing and Energy

  • Energy-aware Compiler and Run-time Tools

  • Data Centers and Resource Management Integration

  • Novel Accelerator Architectures

  • Energy-Efficient Programming models for computing paradigms (e.g., near-threshold computing, approximate computing, or neuromorphic computing)

  • Languages and Compilers for Hardware Accelerators

  • Libraries and Tools to Optimize the Programming of Hardware Accelerators

  • Manual and Automatic Energy Optimization Techniques

  • Benchmarking of Energy Aware Hardware Accelerators

  • Modeling and Performance Prediction for Hardware Accelerators

  • Energy management in operating systems and runtime systems

  • Energy management of the memory sub-systems, displays, and peripherals

  • Energy-efficient Application Development Experience

  • Application-specific Acceleration Hardware/Software

  • Tradeoffs between performance, reliability and energy efficiency

  • Energy-aware Applications using HPC Systems

  • Case Studies

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Important Date
  • Conference Date

    Jul 18

    2016

    to

    Jul 22

    2016

  • Jul 22 2016

    Registration deadline

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