Introduction

The IEEE International High Level Design Validation and Test Workshop aims to stimulate research in and validation and test methodologies for ICs and systems specified using high level descriptions, where high level refers to register-transfer, behavioral, and system level specifications.

Call for paper

Important date

2016-07-30
Draft paper submission deadline
2016-08-15
Draft paper acceptance notification

Submission Topics

  • Simulation-Based Validation
  • Formal Verification, and Hybrid Methods
  • Design Abstraction, and Behavioral Modeling
  • Error Trace Interpretation, and Debugging
  • Functional safety/safety-critical system verification
  • On-Chip, and Core-Based Testing
  • Test Generation for Defects, Design Errors, and Delay Faults
  • Hardware/Software, and Mixed-signal System Co-Validation
  • Emulation, and Prototyping
  • Post-silicon Validation, and Debug.
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Important Date

  • Conference Date

    Oct 07

    2016

    to

    Oct 08

    2016

  • Jul 30 2016

    Draft paper submission deadline

  • Aug 15 2016

    Draft Paper Acceptance Notification

  • Oct 08 2016

    Registration deadline

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IEEE
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