Introduction

The 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2017) will be held in Honolulu, Hawaii, 4-6 June 2017.

The conference starts on Sunday, 4 June 2017 with workshops and short courses, followed by two Plenary talks and Reception embedded with joint Industry Showcase and Interactive Forum. Monday, 5 June and Tuesday, 6 June 2017 will be comprised of presentations of contributed papers and special lunch-time panel sessions.

Call for paper

Important date

2017-01-09
Draft paper submission deadline
2017-02-05
Draft paper acceptance notification
2017-03-16
Final paper submission deadline

Guidlines

  • The conference will solicit papers describing original work in RFIC circuits, system engineering,design methodology, RF modeling and CAD simulation, RFIC technologies, devices, fabrication, testing, reliability,packaging and modules to support RF applications in areas such as, but not limited to:

  • Wireless Cellular & Connectivity ICs: LTE/LTE-Advanced, 5G Massive MIMO, LTE-M, WWAN, WLAN,802.11ax, Bluetooth, GPS

  • Low Power Transceivers: IoT, RFID, NFC, Zigbee, WPAN, WBAN, Biomedical, Sensor Nodes

  • RF Front-End ICs: LNAs, Mixers, Demodulators, VGAs, Filters, Phase shifters, switches, Full-duplex applications, and Interference cancellation

  • Mixed-Signal RF and Analog Baseband Circuits: ADCs, DACs, Sub-sampling/Over- sampling Circuits, and analog baseband circuitry including filters and modulators

  • Reconfigurable and Tunable Front-Ends: Cognitive Radio, Multi-mode advanced cellular radios, Digitallyassisted RF, and Re-configurable blocks (N-path filter, ADCs, tuners)

  • Large-Signal Circuits: Power Amplifiers (RF & mm-Wave), Driver amplifiers, Advanced TX circuits,modulators, efficiency enhancement, and Linearization

  • VCOs and Frequency Multipliers: RF and mm-Wave VCOs, Frequency Multipliers

  • Frequency Generation Circuits: PLLs, Synthesizers, ADPLL, DDS, Frequency Dividers, DLL, and MDLL

  • Modeling, CAD and Testing: RF Design Methodology, RF Modeling and CAD, EM Simulation, Co-Simulation,Testing and Analysis of Active/Passive Devices, and Built-in-Test

  • Process, Device and Packaging Technologies: CMOS, SOI, SiGe, GaAs, GaN, MEMS, Integrated Passives,Photonic, Emerging Devices, Reliability, Packaging, and Modules

  • mm-Wave Circuits & Systems: mmW SOCs and SIPs above 20GHz for data, video, and imaging, mmW frontend circuits, and mmW-based 5G systems

  • High-Speed Data Transceivers: Wireline, UWB, Optical Transceivers, and CDRs for High-Speed Data links 

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Important Date
  • Conference Date

    Jun 04

    2017

    to

    Jun 06

    2017

  • Jan 09 2017

    Draft paper submission deadline

  • Feb 05 2017

    Draft Paper Acceptance Notification

  • Mar 16 2017

    Final Paper Deadline

  • Jun 06 2017

    Registration deadline

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